The present invention relates generally to semiconductor devices and more particularly to methods for sensing data stored in memory cells in memory devices.
Ferroelectric memory devices, and other type semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bitlines, with the other bitline being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of platelines and wordlines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage where data memory cells include capacitors constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a ferroelectric data cell is read by connecting a reference voltage to a first bitline and connecting the cell capacitor between a complimentary bitline and a plateline signal voltage, and interrogating the cell. There are several techniques to interrogate a FeRAM cell. Two most common interrogation techniques are step sensing and pulse sensing. In both these interrogation techniques, the cell capacitor is coupled to the complimentary bitline by turning ON an access or a pass gate. In the step sensing, the plateline voltage is stepped from ground (Vss) to a supply voltage (Vdd). In the pulse sensing the plateline voltage is pulsed from Vss to Vdd and then back to Vss. This provides a differential voltage on the bitline pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (Vxe2x80x9c0xe2x80x9d) associated with a capacitor programmed to a binary xe2x80x9c0xe2x80x9d and that of the capacitor programmed to a binary xe2x80x9c1xe2x80x9d (Vxe2x80x9c1xe2x80x9d). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is buffered and applied to a pair of local IO lines.
The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bitlines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device. In a typical ferroelectric memory read sequence, two sense amp bitlines are initially pre-charged to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp bitlines and interrogated. Thereafter, a reference voltage is connected to the remaining sense amp bitline, and a sense amp senses the differential voltage across the bitlines and latches a voltage indicative of whether the target cell was programmed to a binary xe2x80x9c0xe2x80x9d or to a xe2x80x9c1xe2x80x9d.
In modern memory devices having millions of data cells, there is a continuing need to reduce component sizes and otherwise to conserve circuit area in the device, so as to maximize device density. Accordingly, memory cell layout architectures such as folded bit configurations have been developed to conserve on the amount of die area needed to implement large scale memories, like 64 megabit devices. Such devices are typically divided internally into blocks, sections, segments, rows and columns. For example, a 64M device may include 8 blocks of 8M each, each block may consist of 8 sections of 1M each, each section may be 32 segments, with each segment containing 512 words or rows of 64 bits or columns per word. When a data word is read, the cell data from the corresponding bit in each column is sensed using 64 individual sense amplifiers associated with the individual data cell columns.
FIG. 1 schematically illustrates a segment portion of a memory device 2 having 512 rows (words) and 64 columns (bits) of data storage cells CROW-COLUMN configured in a folded bitline architecture, where each column of cells is accessed via a pair of complimentary bitlines BLCOLUMN and BLCOLUMNxe2x80x2. One column of the device 2 is illustrated in FIG. 2. The cells C1-1 through C1-64 form a data word accessible via a wordline WL1 and complimentary bitline pairs BL1/BL1xe2x80x2 through BL64/BL64xe2x80x2, where cell data is sensed during data read operations using sense amp circuits S/A C1 through S/A C64 associated with columns 1 through 64, respectively. In a typical folded bitline architecture ferroelectric memory device, the cells CROW-COLUMN individually include one or more ferroelectric cell capacitors and one or more access transistors to connect the cell capacitors between one of the complimentary bitlines associated with the cell column and a plateline, where the other bitline is connected to a reference voltage.
In the device 2, the sense amps associated with even numbered columns are located at the bottom of the segment, whereas sense amps associated with odd numbered columns are located at the top of the segment. In order to reduce the number of components in the device 2, as well as to increase device density therein, individual reference voltage generators are not provided for each complimentary bitline pair. Rather, shared reference generators are provided at the top and bottom of the segment columns. An even column reference generator 8 is provided at the bottom of the segment columns to service the sense amps associated with even numbered columns and an odd column reference generator 8xe2x80x2 is provided at the top of the segment columns to service the sense amps associated with odd numbered columns. The reference voltages from the generators 8, 8xe2x80x2 are coupled to one of the bitlines in the columns using one of a pair of switches 8a, 8b, depending upon whether an odd or even numbered target data word is being read.
Sharing the reference generators 8, 8xe2x80x2 across multiple data columns, however, requires the connection of reference bitlines from all the odd numbered columns to one another, and the connection of reference bitlines from all the even numbered data columns together through the activated switches 8a or 8b. In a standard ferroelectric memory read sequence, the complimentary bitlines are precharged or equalized to ground and then left floating. Then, sense bitlines (e.g., the ones of the complimentary bitlines associated with the cell to be accessed) are connected to the target data cells of interest and the cells are interrogated. The reference generators 8, 8xe2x80x2 are then connected to the reference bitlines (the others of the complimentary bitline pairs), so as to establish a differential voltage at the sense amp terminals.
However, due to the physical proximity of the complimentary bitlines to one another, the connection of the sense bitlines to the target cells causes corresponding voltages to be coupled to the floating reference bitlines. These coupled voltages on the reference bitlines depend upon the signal levels on adjacent sense bitlines, including the complimentary sense bitline and the sense bitline from the adjacent column. For example, in reading the first data word of the illustrated segment along wordline WL1 in the device 2, the cells C1-1 through C1-64 are connected to the sense bitlines BL1, BL2 . . . , BL63, and BL64 while the complimentary reference bitlines BL1xe2x80x2, BL2xe2x80x2 . . . , BL63xe2x80x2, and BL64xe2x80x2 are floating. At this point, the induced voltage on the reference bitline BL1xe2x80x2 is a function of the voltages on the adjacent sense bitlines BL1 and BL2. When the reference bitlines BL1xe2x80x2, BL2xe2x80x2 . . . BL63xe2x80x2, and BL64xe2x80x2 are thereafter connected to the reference voltage generators 8, 8xe2x80x2 (with odd column reference bitlines BL1xe2x80x2, BL3xe2x80x2 . . . , and BL63xe2x80x2 connected to one another and even column reference bitlines BL2xe2x80x2, BL4xe2x80x2 . . . , and BL64xe2x80x2 connected to one another), the reference voltages thereon are a function of both the ideal, VREF0, reference generator voltage and the average voltage induced on the connected reference bitlines. The average induced voltage may differ for the even and odd columns, Here the ideal reference generator voltage, VREF0 is referred to as the voltage it would produce on the reference bitlines in the absence of any induced voltage from adjacent bitlines. Note that typically a reference voltage generator is not a perfect voltage source. It is usually based on sharing charges between various capacitors. Any induced voltage or charge on any reference bitline will impact the final voltage, VREF on the reference bitlines.
The voltages on the even and odd reference bitlines is thus not necessarily equal to the ideal value of the voltage generators 8 or 8xe2x80x2 when the bitlines are connected to the sense amp circuits. Rather, the reference bitline voltage is roughly the sum of the ideal reference voltage, VREF0, plus a voltage which is a function of the average voltage induced on the interconnected reference bitlines. Moreover, the voltage on the reference bitlines varies depending upon the data being sensed in the target cells, because the induced voltage is dependent upon the values of the data cells in the data word being read.
The offset and variability in the value of voltage at the reference terminal of the sense amp circuit reduces the sense margin for ascertaining the value of data stored in the ferroelectric memory cells. Bitline twist techniques have been used to reduce the cross coupling between sense bitlines and reference bitlines during read operations. However, these layout techniques are not perfect and result in only marginal improvement, and may also be difficult to implement, particularly while reducing device sizes and increasing device densities in memory devices. Thus, there is a need for improved apparatus and methods for sensing data stored in ferroelectric memory cells by which adverse effects of cross-coupled reference bitline voltages can be reduced or mitigated alone or in combination with such bitline twist approaches.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention provides memory devices comprising one or more memory cells, such as ferroelectric memory cells connected to one of first and second data bitlines and a reference connected to another of the first and second data bitlines during a read operation. A sense amp and a precharge circuit are provided, where the precharge circuit couples one sense amp bitline to a precharge voltage while the other sense amp bitline is connected to the ferroelectric memory cell. This may be employed, for example, to discharge induced voltages from the reference bitlines due to connection of memory cells to the adjacent sense bitlines during a memory read operation. In one implementation, the reference and sense bitlines of the sense amp circuit are initially coupled to the precharge voltage, such as VSS or ground, and thereafter the sense bitlines are connected to the data cells while the reference bitlines are held at VSS. With the reference bitlines thus maintained at a constant potential, the induced charge associated with connection of the sense bitlines to the ferroelectric data cells is discharged to ground.
Thereafter, the reference bitlines are decoupled from the precharge voltage and connected to the reference generators, and the sense amp circuit senses the differential voltage applied across the sense amp bitlines. Since the induced voltage resulting from the sense bitline connection with the cells is dissipated before connecting the reference voltage generator, the sense margin of the sense amp circuit is not impacted by the coupling between reference bitlines and adjacent sense bitlines. Thus, the invention may be employed to reduce or avoid reference bitline offset problems experienced in conventional designs. Moreover, the invention may be employed to reduce the variance in the reference bitline voltage, since the variation in the data stored in the target cells of interest no longer affects the reference bitline voltage value. In the new technique there may be coupling from the reference bitlines to the sense bitlines when the reference voltage is generator is coupled to the reference bitlines. However, this coupling will be same for all the sense bitlines and is of less concern.
Another aspect of the invention provides methods for sensing data from a ferroelectric or other type memory cell in a memory device, comprising coupling a first sense amp bitline to the memory cell while a second sense amp bitline is coupled to a precharge voltage, and thereafter decoupling the second sense amp terminal and coupling the second sense amp bitline with a reference. The methods of the invention may be employed to reduce or mitigate the effects of cross-coupled bitline voltages in ferroelectric and other type memory devices, alone or in combination with interconnection layout techniques such as twisted bitline approaches.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative-aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.